1. Field of the Invention
This invention relates generally to automatic test equipment used to test integrated circuit elements, and more particularly to interface hardware used in automatic test equipment to connect devices under test to a test head in order to perform the testing.
2. Description of the Related Art
Automatic test equipment (i.e., a tester) is generally used to test semiconductor devices and integrated circuit elements, such as memory or logic for manufacturing defects. A general representation of a tester is shown in FIG. 1. As shown, a tester 1 has a tester body 10, which is in communication with a test head 20. The test head 20 is in communication with devices under test (DUTs) 60 via an interface 30. The DUTs 60 are the various integrated circuit elements being tested. In this way, multiple DUTs 60 can be tested rapidly and simultaneously. Further, after a group of DUTs 60 are tested, a new group of DUTs 60 are introduced for testing using a handler 5.
As shown in FIGS. 2 and 3, the DUTs 60 are arrayed on DUT boards 80. The DUT boards 80, also known as socket boards, device interface boards, and load boards, are on respective board spacers 40, which rest on a spacing frame 50. The board spacers 40 are hollowed in the center to allow cables 70 to be attached to the DUT boards 80. Each DUT 60 is connected to a respective cable 70 through solder-lined through holes 83 in the DUT board 80, with the actual connection being at solder point 82. As such, each cable 70 is solder connected, individually, to the DUT board 80.
For a conventional tester 1, when a new type of DUT 60 is to be tested, the new DUT 60 is brought to the tester 1 via handler 5 and connected to a test socket (not shown), completing the electrical connection between the test head 20 and the new DUT 60. The test is then performed. After completion of the test, the DUT 60 is then removed from the test socket via handler 5, and a new DUT 60 of the same type is installed into the test socket using the handler 5.
If a new type of DUT 60 is to be tested, the old DUT board 80 must be replaced and a new DUT board 80 inserted in its place. The new DUT board 80 will have different connection needs reflecting the new type of DUT 60. As such, either a new interface assembly must be used, or the cables 70 must be resoldered at different solder points 82. In either case, the cables 70 are custom fitted to different DUT boards 80 for each new type of DUT 60 to be tested. Further, where the cables 70 are resoldered, each change in DUT 60 type requires that the interface assembly, including the board spacer 40, be partially or wholly disassembled, the cables 70 be soldered onto respective solder points 82 of the new DUT board 80, and the interface be reassembled. On the other hand, where the entire interface assembly is replaced, large numbers of interface assemblies must be stored for each type of DUT 60 to be tested.
This use of solder connections is problematic since it is time consuming to attach the cables 70 to the solder points 82 of the DUT boards 80. This problem is exacerbated as both the density and/or number of DUTs 60 increases. For instance, modern testers can accommodate up to 128 DUTs 60 per test head 20, with changes in the types of DUTs 60 being made multiple times per week, or even per day. As such, the requirement that the interface be disassembled and reassembled, and the custom soldering to connect the cables 70 to the different types of DUT boards 80 can require significant time and expense to perform for each change in the type of DUT 60 to be tested, and also significantly increases the amount of time required to test the DUT 60s.
As shown in FIG. 4A, one solution to the limitations of solder connection has been to utilize spring loaded pogos 100, such as the pogo pin produced by Everett Charles, which rest on respective pogo boards 110. The pogos 100 include an internal spring that allows the top half of the pin 100 to be biased against a pad 90 on the DUT board 80, thus forming a communication pathway to a respective DUT 60. Using this system, when a new type of DUT 60 is to be tested, the cables 70 do not have to be soldered to the DUT board 80. Instead, the cables 70 remain soldered to the pogo boards 110, and the new DUT board 80 is placed on the pogo board 110 such that the pins 100 are biased against respective pads 90 to form the communication pathways. As such, the entire interface does not have to be changed.
However, this solution also is problematic as the number and density of DUTs 60 being tested increases. As the density of DUTs 60 being tested increases, smaller and smaller pogos 100 must be used in order to fit into the space provided under the DUT board 80. As the pogos 100 get smaller, they become more delicate and difficult to work with. Further, as pogos 100 get smaller, their stroke (i.e., the distance that the tip of the pin 100 can travel vertically in order to bias against pad 90) decreases, which means that the DUT board 80 and the pogo boards 110 must be made highly planar to ensure a connection at all pads 90. This increases the production cost for the pogo boards 110 and the DUT boards 80. In addition, pogos 100 are themselves expensive to use. As such, pogos 100 do not present an ideal alternative to solder connection as the density and/or number of DUTs 60 increases.
Where the DUT 60 is a logic element 65, it is known to perform lower parallelism testing using plugs 160 as shown in FIGS. 4B and 4C. For logic elements, the cables 70 are soldered into daughter boards within plugs 160. The plugs 160, such as the Micopax plug produced by FCI, are held by a plug holder 180, and are connected to respective receptacles 170. The receptacles 170 are connected to a logic board 150. In this way, instead of directly solder-connecting the cables 70 to the logic board 150, the plugs 160 are received by receptacles 170 located on the logic board 150. Not all of the plugs 160 are used for each type of logic element 65 tested.
However, this configuration is known for use in lower-parallelism testing of logic elements 65, and requires the use of eight or more plugs 160 per logic board 150. Such a configuration is unsuitable for high-density, high-parallelism testing of DUTs, especially where the DUT is a smaller device such as a memory device. In order to test these devices, the DUT boards are smaller, which prevents the use of numerous plugs 160. Further, the handlers 5 that move the memory devices, such as the Advantest M65XX and M67XX series handlers, use spacing frames having a pitch that does not allow the use of a large number of plugs 160 in order to test these devices. Thus, for high-parallelism testing of memory devices (i.e., simultaneous testing of 32 or more devices), conventional plug arrangements were not possible.
It is an object of the invention to provide a connection system between devices under test and a test head that provides a secure modular connection to the devices under test for high data rates without causing degradation in signal quality.
It is a further object of the invention to provide a high density, scalable connection system between devices under test and a test head.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Accordingly, to achieve these and other objects, an embodiment of the present invention uses an interface between a device under test (DUT) and cables, including a first board having an array of first connectors, each first connector connected to a respective cable, and a second board holding the DUT and having second connectors, each second connector being connected to the DUT and to a respective first connector, and where the number of second connectors is less than the number of first connectors.
According to another embodiment of the invention, the first connectors and second connectors comprise pairs of header connectors and shielded-controlled impedance connectors.
According to a further embodiment of the invention, the first connectors and the second connectors comprise pairs of pads allowing a board-to-board connection between the first board and the second board.
According to another embodiment of the present invention, an interface to perform high-parallelism testing of memory devices comprises a first board holding one of the memory devices and having a receptacle connected to the one memory device, and a plug connected to respective cables and to the receptacle to create a communication pathway, wherein combinations of the first boards and the plugs allow high-parallelism testing of the memory devices.
According to a still further embodiment of the present invention, a method of connecting a DUT on a DUT board to cables for testing comprises unplugging a first DUT board having a first number of connectors from respective cables held in an array on a board spacer, and plugging a second DUT board having a second number of connectors different from the first number of connectors into the cables.
According to yet another embodiment of the present invention, a method of connecting a DUT on a DUT board to cables for testing comprises removing a first DUT board having first pads connected to a first DUT from a board spacer having board pads connected to the cables, where respective pairs of first pads and board pads formed a board-to-board connection creating first communication pathways for signals between the cables and the first DUT, and placing a second DUT board having second pads connected to a second DUT onto the board spacer to form a board-to-board connection creating a second communication pathways for signals between the cables and the second DUT.
According to still another embodiment of the present invention, a method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices that comprises unplugging a first DUT board having a first receptacle from a plug connected to respective cables, and plugging a second DUT board having a second receptacle into the plug to form a communication pathway between the memory device and the cables, wherein combinations of the second DUT boards and the plugs allow high-parallelism testing of the memory devices.